1. Field of the Invention
The present invention relates to a memory device with a nonvolatile memory array, in particular an electrically erasable programmable read only memory (EEPROM) array field or an electrically programmable read only memory (EPROM) array field.
2. Description of the Background Art
Electrically erasable programmable read only memories are known by the abbreviation EEPROM or E2PROM. EEPROMs that use programming by injection of hot charge carriers in place of programming by tunneling based on Fowler-Nordheim are known from U.S. Pat. No. 4,698,787 or DE 695 22 738 T2, which corresponds to U.S. Pat. No. 5,412,603, for example.
From U.S. Pat. No. 7,023,738, a circuit for driving a column/row of nonvolatile memory is known. Potential shifters are used for shifting a logic value of a corresponding selection signal to a bias voltage, and a selector is used for applying a first operative signal or a second bias voltage to a memory line according to the second operative signal.
In a method for programming memory cells as shown in FIGS. 1 and 2 using hot channel techniques for programming a cell by injection of hot charge carriers, a high voltage is applied to the control gate. During programming of a selected cell by the injection of hot charge carriers, the voltages applied to the source, drain and control gate are as follows: a reference voltage applied to the source, which is equal to the substrate voltage (VSS, which may be 0 volts); a first positive voltage VBL of approximately +5 to +7 V with respect to the reference voltage, applied to the drain; and a second positive voltage VPP with respect to the reference voltage, applied to the control gate.
Under these conditions, the channel between the drain and the source is highly conductive. Electrons that reach the substrate/drain PN junction are subjected to two electric fields in the array (EEPROM), one of which is associated with the substrate/drain PN junction, which is biased in the reverse direction, and the other of which is associated with the positive voltage between the control gate and the floating gate.
The electric field in the array produced in the silicon substrate in the vicinity of the substrate/drain PN junction and the interface to the floating gate is the primary factor in determining programmability by injection of hot charge carriers in memories with floating gates such as EPROM and flash EPROM array fields. The electric field in the array depends primarily on the drain-to-source potential, but also includes other parameters such as the doping profiles of the channel zone and the drain zone.
One type of memory array field with floating gate requires both a 5 volt power supply and a 12 volt power supply as supply potentials. In such dual-supply memories, the 12 volt voltage is used to supply the +5 V to +7 V drain voltage VBL that is necessary during programming. Another type of memory array field with floating gate requires a single 5 V supply. In this single-supply memory, the 5 volt power supply is pumped through a charge pump circuit in order to supply a drain voltage VBL that is greater than +6 V during programming.
According to DE 695 22 738 T2, a charge pump circuit can be used which pumps the source of a selected cell to a voltage that is smaller than the voltage at the reference terminal of the integrated memory circuit. At the same time, the drain potential of the selected cell is pumped to a voltage that is greater than the voltage at the supply voltage terminal of the memory.
For example, in DE 695 22 738 T2, a drain-to-source voltage of approximately 6 V is achieved from a 3 V supply by using a charge pump circuit which pumps the source voltage to approximately 1.5 V below the voltage at the reference terminal of this 3 V supply and simultaneously pumps the drain voltage to 1.5 V above the voltage at the positive terminal of this 3 V supply. The charge pump circuit can also be used to pump the cell substrate voltage to a value that is close to or smaller than the source voltage. To increase the effectiveness of the programming, the cell substrate voltage is pumped to a value smaller than the source voltage.
Shown in FIG. 1 in order to illustrate the prior art is an array field (EEPROM) of memory cells which are integrated in a memory component. Each cell is a transistor 10 with a source 11, a drain 12, a floating gate 13 and a control gate 14. Each control gate 14 of a row of cells 10 is connected to a word line 15, while each word line 15 is connected to a word line decoder 16.
Each source 11 in a row of cells 10 is connected to a source line 17. Each drain 12 in a row of cells 10 is connected to a drain column line 18. Each source line 17 is connected to a column decoder 19 through a line 17a common to the columns, and each drain column line 18 is connected to the column decoder 19.
In read mode, the word line decoder 16 is used to apply—in response to word line address signals through the lines 20R and signals from the read/write/erase control circuit 21, which can be a microprocessor, for example—a predefined positive potential VCC (approximately +5 V) to the selected word line 15 and to apply a low potential (ground or VSS) to the deselected word lines 15.
The column decoder 19 is used to apply a predefined positive potential VSEN (approximately +1 V) to at least the selected drain column line 18 and to apply a low potential (0 V) to the source line 17. The column decoder 19 is also used to connect the selected drain column line 18 of the chosen cell 10 to the data input/data output terminal 22 in response to signals over the address lines 20D. The conductive or nonconductive state of the cell 10 connected to the selected drain column line 18 and to the selected word line 15 is detected by a read amplifier (not shown in FIG. 1) that is connected to the data input/data output terminal 22.
In flash erase mode, the column decoder 19 can be used to drive all drain column lines 18 into a floating state (to connect to a high impedance, such as array field effect transistors that are biased in an OFF state). The word line decoder 16 serves, for example, to connect all word lines 15 to a negative potential VEE (for instance, −10 V or −13 V). The column decoder 19 is additionally used to apply a positive potential VCC (for instance, +5 V or +3 V) to all source lines 17.
The substrate insulation well W2 from FIG. 2 of DE 695 22 738 T2 is connected to VSS or 0 V by a substrate control circuit 23. The word line decoder 16 is used to connect all word lines 15 to a negative potential VEE (approximately −9 V).
The column decoder 19 is also used to connect all source lines 17 and all drain lines 18 to +6 V. The substrate insulation well W2 is likewise connected to +6 V here. These erase voltages between the potentials produce sufficient field strength across the gate oxide zone to generate a Fowler-Nordheim tunneling current that transfers charge from the floating gate 13, causing the memory cell 10 to be erased. Since the potential on the word line 15 is negative, the cell 10 remains in the nonconductive state during the erasure.
In the write, or program, mode from DE 695 22 738 T2, the word line decoder 16 may serve, in response to word line address signals on the lines 20R and to signals from the read/write/erase control circuit 21, to place a predefined first programming potential VPP (approximately +12 V) on a selected word line 15, including a selected control gate 14. The column decoder 19 also serves to place a second programming potential VBL (approximately +5 V to +10 V) on a selected drain column line 18 and, therefore, the drain 12 of the selected cell 10.
In the circuit from FIGS. 1 and 2 of this prior art technology, the source lines 17 are connected to, for example, the reference potential VSS, which may be ground. All of the deselected drain column lines 18 are connected to the reference potential VSS or are floated. On account of these potential differences, the programming voltages create a high current (drain 12 to source 11) condition in the channel of the selected memory cell 10, resulting in the generation near the drain/channel junction of hot channel electrons and avalanche-breakdown electrons that are injected across the channel oxide to the floating gate 13 of the selected cell 10.
The programming time is selected to be sufficiently long to program the floating gate 13 with a negative programming charge of approximately −2 V to −6 V with respect to the channel region (with the control gate 14 at 0 V). For this reason, the prior art programming potential VPP of 12 V, for example, on a selected word line 15, including the selected control gate 14, places a potential of approximately +7.2 V on the selected floating gate 13.
The voltage between the floating gate 13 (at approximately +7.2 V) and the grounded (approximately 0 V) source line 17 is insufficient to cause a Fowler-Nordheim tunneling current across the gate oxide between a source 11 and a floating gate 13 to charge the floating gate 13 of a selected or deselected cell 10. The floating gate 13 of the selected cell 10 is charged with hot electrons injected during programming, and the electrons in turn render the source-drain path under the floating gate 13 of the selected cell 10 nonconductive with +5 V on its control gate 14, a state which is read as a “zero” bit. Unprogrammed cells 10 have source-drain paths under the floating gate 13 that are conductive with +5 V on their control gates 14, and those cells 10 are read as “one” bits.
In the write, or program, operation according to the prior art shown in FIGS. 1 and 2, the drain-to-source potential required for programming is achieved by using a charge pump circuit to pump the source 11 of the selected cell 10 to a potential VSL about −1 V to −2 V below the potential VSS at the negative terminal of the supply (perhaps 3 V) while, at the same time, pumping the drain 12 of the selected cell 10 to a potential VBL of approximately +6 V above the potential at the source.
At the same time, a substrate potential VSUB of a substrate isolation well W2 in the substrate 24 is connected by a substrate control circuit 23 to either the potential VSUB, which may be the same potential VSL as the source 11, or to a more negative value of about −2 V to −3 V below the potential VSS at the negative terminal of the power supply. The substrate isolation well W2 must isolate at least each selected cell 10 or the entire memory cell array field.
Programming of the selected cell 10 by hot charge carrier injection is achieved by applying a pulse from VPP of about +10 V on the gate 14 of the selected cell 10. The deselected word lines are connected to VSS or 0 V, or to a potential about −1 V to −2 V with respect to VSS to prevent leakage losses through deselected cells.